All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18F14K50
CONFIG1L (address:0x300000, mask:0x38, default:0x00)
CPUDIV -- CPU System Clock Selection bits (bitmask:0x18)
CPUDIV = NOCLKDIV 0xE7 No CPU System Clock divide.
CPUDIV = CLKDIV2 0xEF CPU System Clock divided by 2.
CPUDIV = CLKDIV3 0xF7 CPU System Clock divided by 3.
CPUDIV = CLKDIV4 0xFF CPU System Clock divided by 4.
USBDIV -- USB Clock Selection bit (bitmask:0x20)
USBDIV = OFF 0xDF USB clock comes directly from the OSC1/OSC2 oscillator block; no divide.
USBDIV = ON 0xFF USB clock comes from the OSC1/OSC2 divided by 2.
CONFIG1H (address:0x300001, mask:0xFF, default:0x27)
FOSC -- Oscillator Selection bits (bitmask:0x0F)
FOSC = LP 0xF0 LP oscillator.
FOSC = XT 0xF1 XT oscillator.
FOSC = HS 0xF2 HS oscillator.
FOSC = ERCCLKOUT 0xF3 External RC oscillator, CLKOUT function on OSC2.
FOSC = ECCLKOUTH 0xF4 EC, CLKOUT function on OSC2 (high).
FOSC = ECH 0xF5 EC (high).
FOSC = ERC 0xF7 External RC oscillator.
FOSC = IRC 0xF8 Internal RC oscillator.
FOSC = IRCCLKOUT 0xF9 Internal RC oscillator, CLKOUT function on OSC2.
FOSC = ECCLKOUTM 0xFA EC, CLKOUT function on OSC2 (medium).
FOSC = ECM 0xFB EC (medium).
FOSC = ECCLKOUTL 0xFC EC, CLKOUT function on OSC2 (low).
FOSC = ECL 0xFD EC (low).
PLLEN -- 4 X PLL Enable bit (bitmask:0x10)
PLLEN = OFF 0xEF PLL is under software control.
PLLEN = ON 0xFF Oscillator multiplied by 4.
PCLKEN -- Primary Clock Enable bit (bitmask:0x20)
PCLKEN = OFF 0xDF Primary clock is under software control.
PCLKEN = ON 0xFF Primary clock enabled.
FCMEN -- Fail-Safe Clock Monitor Enable (bitmask:0x40)
FCMEN = OFF 0xBF Fail-Safe Clock Monitor disabled.
FCMEN = ON 0xFF Fail-Safe Clock Monitor enabled.
IESO -- Internal/External Oscillator Switchover bit (bitmask:0x80)
IESO = OFF 0x7F Oscillator Switchover mode disabled.
IESO = ON 0xFF Oscillator Switchover mode enabled.
CONFIG2L (address:0x300002, mask:0x1F, default:0x1F)
PWRTEN -- Power-up Timer Enable bit (bitmask:0x01)
PWRTEN = ON 0xFE PWRT enabled.
PWRTEN = OFF 0xFF PWRT disabled.
BOREN -- Brown-out Reset Enable bits (bitmask:0x06)
BOREN = OFF 0xF9 Brown-out Reset disabled in hardware and software.
BOREN = ON 0xFB Brown-out Reset enabled and controlled by software (SBOREN is enabled).
BOREN = NOSLP 0xFD Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled).
BOREN = SBORDIS 0xFF Brown-out Reset enabled in hardware only (SBOREN is disabled).
BORV -- Brown-out Reset Voltage bits (bitmask:0x18)
BORV = 30 0xE7 VBOR set to 3.0 V nominal.
BORV = 27 0xEF VBOR set to 2.7 V nominal.
BORV = 22 0xF7 VBOR set to 2.2 V nominal.
BORV = 19 0xFF VBOR set to 1.9 V nominal.
CONFIG2H (address:0x300003, mask:0x1F, default:0x1F)
WDTEN -- Watchdog Timer Enable bit (bitmask:0x01)
WDTEN = OFF 0xFE WDT is controlled by SWDTEN bit of the WDTCON register.
WDTEN = ON 0xFF WDT is always enabled. SWDTEN bit has no effect.
WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x1E)
WDTPS = 1 0xE1 1:1.
WDTPS = 2 0xE3 1:2.
WDTPS = 4 0xE5 1:4.
WDTPS = 8 0xE7 1:8.
WDTPS = 16 0xE9 1:16.
WDTPS = 32 0xEB 1:32.
WDTPS = 64 0xED 1:64.
WDTPS = 128 0xEF 1:128.
WDTPS = 256 0xF1 1:256.
WDTPS = 512 0xF3 1:512.
WDTPS = 1024 0xF5 1:1024.
WDTPS = 2048 0xF7 1:2048.
WDTPS = 4096 0xF9 1:4096.
WDTPS = 8192 0xFB 1:8192.
WDTPS = 16384 0xFD 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3H (address:0x300005, mask:0x88, default:0x88)
HFOFST -- HFINTOSC Fast Start-up bit (bitmask:0x08)
HFOFST = OFF 0xF7 The system clock is held off until the HFINTOSC is stable.
HFOFST = ON 0xFF HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
MCLRE -- MCLR Pin Enable bit (bitmask:0x80)
MCLRE = OFF 0x7F RA3 input pin enabled; MCLR disabled.
MCLRE = ON 0xFF MCLR pin enabled; RA3 input pin disabled.
CONFIG4L (address:0x300006, mask:0xCD, default:0x85)
STVREN -- Stack Full/Underflow Reset Enable bit (bitmask:0x01)
STVREN = OFF 0xFE Stack full/underflow will not cause Reset.
STVREN = ON 0xFF Stack full/underflow will cause Reset.
LVP -- Single-Supply ICSP Enable bit (bitmask:0x04)
LVP = OFF 0xFB Single-Supply ICSP disabled.
LVP = ON 0xFF Single-Supply ICSP enabled.
BBSIZ -- Boot Block Size Select bit (bitmask:0x08)
BBSIZ = OFF 0xF7 1kW boot block size.
BBSIZ = ON 0xFF 2kW boot block size.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF 0xBF Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON 0xFF Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON 0x7F Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug.
DEBUG = OFF 0xFF Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x03, default:0x03)
CP0 -- Code Protection bit (bitmask:0x01)
CP0 = ON 0xFE Block 0 code-protected.
CP0 = OFF 0xFF Block 0 not code-protected.
CP1 -- Code Protection bit (bitmask:0x02)
CP1 = ON 0xFD Block 1 code-protected.
CP1 = OFF 0xFF Block 1 not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)
CPB -- Boot Block Code Protection bit (bitmask:0x40)
CPB = ON 0xBF Boot block code-protected.
CPB = OFF 0xFF Boot block not code-protected.
CPD -- Data EEPROM Code Protection bit (bitmask:0x80)
CPD = ON 0x7F Data EEPROM code-protected.
CPD = OFF 0xFF Data EEPROM not code-protected.
CONFIG6L (address:0x30000A, mask:0x03, default:0x03)
WRT0 -- Table Write Protection bit (bitmask:0x01)
WRT0 = ON 0xFE Block 0 write-protected.
WRT0 = OFF 0xFF Block 0 not write-protected.
WRT1 -- Table Write Protection bit (bitmask:0x02)
WRT1 = ON 0xFD Block 1 write-protected.
WRT1 = OFF 0xFF Block 1 not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)
WRTC -- Configuration Register Write Protection bit (bitmask:0x20)
WRTC = ON 0xDF Configuration registers write-protected.
WRTC = OFF 0xFF Configuration registers not write-protected.
WRTB -- Boot Block Write Protection bit (bitmask:0x40)
WRTB = ON 0xBF Boot block write-protected.
WRTB = OFF 0xFF Boot block not write-protected.
WRTD -- Data EEPROM Write Protection bit (bitmask:0x80)
WRTD = ON 0x7F Data EEPROM write-protected.
WRTD = OFF 0xFF Data EEPROM not write-protected.
CONFIG7L (address:0x30000C, mask:0x03, default:0x03)
EBTR0 -- Table Read Protection bit (bitmask:0x01)
EBTR0 = ON 0xFE Block 0 protected from table reads executed in other blocks.
EBTR0 = OFF 0xFF Block 0 not protected from table reads executed in other blocks.
EBTR1 -- Table Read Protection bit (bitmask:0x02)
EBTR1 = ON 0xFD Block 1 protected from table reads executed in other blocks.
EBTR1 = OFF 0xFF Block 1 not protected from table reads executed in other blocks.
CONFIG7H (address:0x30000D, mask:0x40, default:0x40)
EBTRB -- Boot Block Table Read Protection bit (bitmask:0x40)
EBTRB = ON 0xBF Boot block protected from table reads executed in other blocks.
EBTRB = OFF 0xFF Boot block not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2014-07-23 18:35:48 UTC) from the 8bit_device.info file (rev: 1.20) of mpasmx and from the gputils source package (rev: svn 1078). The mpasmx is included in the MPLAB X.